Segmentation architecture

• logical address: consists of two-tuple
  • segment-number, offset
• segment table: maps 2D programmer-defined address into 1D physical address
  • each entry: contains:
    • base: containing starting physical address of each segment
    • limit: specifying length of segment
• both STBR / STLR: stored in PCB of a process
  • segment-table base register (STBR): points to segment table's location in memory
  • segment-table length register (STLR): indicating no. of segments used by program
• segment no. $s$: legal if $s<STLR$
• protection: each entry in segment table associating w/
  • validation bit = 0: illegal segment
    • 👨‍🏫 part of protection bit
  • read / write / execute privileges
• 
• protection bit: associated w/ each segment
  • code sharing: occurring at segment level
• each segment: vary in length
  • thus dynamic storage allocation problem still exists
  • yet, much less severe as each segment: considerably smaller than entire memory space
• process: might share data
  • simply use same base & limit in segmentation table for shared segment!
  • 

Summary segmentation

• protection: easy in segment table
  • code segment: read-only
  • data & stack: read-write, etc.
• address: can be outside valid range
  • as stack & heap: allowed to grow
  • system automatically increase the size of stack
• main program w/ segmentation
  • dynamic storage allocation problem and external fragmentation persists
  • may move processes multiple times to fit everything
  • from processor view: good & easy

Paging

• divide physical memory into fixed-sized blocks: frames
  • usually power of 2: between 4 KB (12 bit offset) to 1 GB (30 bit offset)
    • defined by the hardware
  • 👨‍🏫 frame number: unique in physical address
• divide logical memory into: blocks of same-size pages (same size as frame)
  • OS: keep track of all free (physical) frames available in main memory
• to run program of size $N$ pages: find $N$ free frames (non-contiguous) in memory
• page table: used for translating logical to physical address
  • yet: suffers from internal fragmentation in last page / frame

Address translation scheme

• address generated by CPU: 2 parts
  • page number (p): index for page table
    • containing base address of each page in physical memory
  • page offset (d): combined w/ base address to define physical memory

• page size / frame size: fixed
• same for size of page
• for $m$ bits logical address, logical address space: $2^m$ bytes
  • if page size / frame size $2^n$
  • no. of pages: $2^{m-n}$
• example
  • let page no. $20$-bit, page off set $12$-bit
  • then page size: $2^{12}=4$ KB
  • 32 bit virtual address: shows $2^{32}=4$ GB
  • 20 bits for page no.: no. of pages $=2^{20}$

Paging hardware

• steps:
  1. extract page no. $p$ and use it for page table index
  2. extract corresponding frame no. $f$ from page table
  3. replace page no. $p$ with frame no. $f$
• 
• offset $d$: doesn't change, but replaced
  • frame no. & offset: not gives physical address

Paging example

• 
• frame no.: automatically derive from starting address of each frame
• $m=4$: means logical address of $2^4=16$ bytes
• logical address $0$: page 0 & offset 0
  • page 0 = frame 5 (from table)
  • logical address 0: physical address 5<<n + 0 = 20
  • logical address 3=(0,3): physical address 5<<n + 3 = 23
  • logical address 4=(1,0): physical address 6<<n + 0 = 24
  • logical address 13=(3,1): physical address 2<<n + 1 = 9
• $n=2$: each page size: $2^2=4$ bytes
• calculating internal fragmentation
  • page size: 2,048 bytes (2KB)
  • process size: 72,766 bytes
  • 35 pages + 1086 bytes
  • internal fragmentation: 2,048 - 1,086 = 962 bytes
  • worst case fragmentation: 1 frame - 1 byte
  • average fragmentation: 1/2 frame
• is small frame: desirable?
• page size: grown over time
  • SubMicro Solaris: support 8 KB and 4 MB
• process & physical memory view: very different
  • for programmer: memory is contiguous
    • actually: no

Implementation of page table

• page table: in main memory
  • PCB: keep track of memory allocation for process
  • page-table base register (PTBR):
  • page-table length register (PTLR):
• under the scheme: every data / instruction access requires two memory access

• one for page table (translation) and another for fetching data
• associative memory / translation look-aside buffers

Associative memory

• a parallel search
• address translation $(p,d)$
  • check all entries in parallel
    • TLB: shared & used by all processes
    • (w/ PID and page number)
  • if $p$: in associative register: get frame no. out: (TLB hit)
  • else: bring the entry to TLB / memory
• locality on TLB
  • instruction: usually stays on the same page (sequential access nature)
  • stack: exhibits locality (pop in & out)
  • data: less locality, still quite a bit

Paging hardware w/ TLB